High density dynamic random access memory (DRAM) products and integrated circuit products typically employ transistor arrays. The reliable-management of the electrical environment of these arrays becomes increasingly challenging with the increase in number and density (decreased channel length and channel width) of memory array devices. The electrical environment of the array devices is naturally important to the ability of the devices to be operated for their intended purpose, e.g., in the case of a memory array, writing, reading and retaining data in the individual cells of the array.
As shown in FIG. 1, a typical DRAM memory cell of a memory array contains an FET transfer transistor 10 which interfaces with a charge storage device (capacitor) 60 which stores the data state of the cell. The array transfer transistor 10 typically has a gate 40 (in the case of DRAM connected to a word line) which is passivated by a dielectric insulator 70. The drain 20 of array transfer transistor 10 acts as a path to charge storage device 60. Source 30 of array transfer transistor 10 acts as a bit line contact path (e.g., a path to allow sensing of the voltage in capacitor 60). Drain 20 and source 30 are separated by well (or body) 50.
A primary consideration in the cell transistor operating environment (e.g., range of conditions where the cell is reliable) is leakage current. Leakage may result in cell or product fails, excess power consumption, and/or constrained operating conditions (e.g., need for tight voltage regulation, wider spacing of components, increased redundancy, etc.).
In the cell of FIG. 1, the leakage current may occur along several paths. For example, transistor off-state (subthreshold) leakage current A may occur between drain 20 and source 30 along the channel. Junction leakage current B may occur between drain 20 and substrate (body or well) 50 induced by the substrate (body or well) bias. Gate-Induced-Drain-Leakage (GIDL) current C may also occur between drain 20 and the substrate (body or well) 50 induced by the gate bias. The performance of the DRAM array cells may thus be adversely affected if the electrical environment is not effectively controlled. Unfortunately, this control becomes more problematic with decreasing device dimensions, i.e., when channel lengthen is further reduced.
Generally, the electrical operating environment of the cell is defined by bias conditions of the transfer transistors which are selected to establish the operating window for the processes to be performed reliably by the chip circuitry during normal operation (e.g., the read, write and other operations). For example, to achieve certain word-line access speed, the word-line boost level (or V.sub.pp) is set to have sufficient gate overdrive. On the other hand, too much overdrive will damage the gate dielectric and cause reliability concern. Also, in order to reduce the cell leakage, the negative word-line level is set properly below ground so that the transfer transistors are turned off more hardly for those non-selected word-lines. However, if biased too much, then the GIDL leakage will dominate the leakage mechanism and result in poor retention situation. Similarly, the body bias, V.sub.bb, is also implemented to cut down the subthreshold leakage. Excessive body bias will cause junction leakage to increase and would result in unsatisfied retention.
Largely for economic reasons, the bias conditions are set during design stage and can be slightly adjusted at the wafer-level burn-in. With an array containing thousands of cells, selecting the appropriate bias conditions may be difficult due to lack of uniformity of cells across the wafer, from wafer to wafer and from lot to lot. In other words, a single set of bias conditions will be difficult to cope with non-uniform threshold voltage distribution across the wafer.
The nominal bias conditions for the cell array are typically selected based on the intended cell geometry and performance characteristics assuming all cells act the same; this assumption breaks down as arrays become larger and cell sizes (ground rules) become smaller. Thus, slight variations in the geometry or manufacturing condition across the array on the chip and/or across the wafer will cause increasingly wider variations in the electrical characteristics (e.g. threshold voltage (V.sub.t) of array transfer transistor) among the cells of the array. For example, variations in the planarity of adjacent shallow trench isolation (STI) can cause array V.sub.t variations as large as 200 mV across a wafer. Variations in array V.sub.t may directly translate into degradation of the retention time for the DRAM circuit due to certain array transistors having significant transistor off-state leakage current. The increasingly wide variations in the array V.sub.t, make it difficult to obtain a robust design with a fixed bias set, such as a fixed V.sub.bb (body bias), V.sub.pp (word line boost voltage), or V.sub.nwll (negative word line low). Thus, the yield of DRAM chips from the wafer and/or the performance of those chips may be compromised.
In the past, this problem has been addressed to some extent by various bias correction techniques to improve the retention time of memory array by optimizing the critical operating voltage conditions. Earlier approaches include tuning the body bias at the end of the product development stage, or by holding the gate of the non-active transfer devices below ground. These approaches tend to over adjust the voltage conditions, and therefore lead to negative impact to the device performance and circuit power consumption. For example, the over-correction of the substrate bias may result in failure of other cells due to increases in junction leakage at high substrate biases. Another example is that the over-adjustment of the gate bias of the non-active transfer devices below ground can also lead to fails in other cells due to increases in gate-induced drain leakage (GIDL) at high off-state gate biases as has mentioned above. Also, the monitor devices used in the past have typically provided wrongful and misleading information regarding the real product array due to mismatch between the dimensions of monitor devices used and those of the real product array.
Thus, there is a need for improved bias correction techniques and on-chip support circuits which enable improved bias control and correction to achieve improved chip operation and yield even for memory arrays on the order of 1 giga byte or higher. It would be especially desirable to provide such improvements to enable proper biasing of the chip which can be trimmed at the wafer level burn-in.